The Development of Systolic Processor Arrays for Pattern Recognition, Image, and Signal Processing at the Universities of Heidelberg and Mannheim - a Status Report

This paper describes three systolic array processors. Two of them have been designed for high-speed pattern recognition and the third for general purpose image and signal processing applications. The two pattern recognition systems operate on pixel images and execute the recognition process within 5 μs to 20 μs. The patterns which are recognized are simple geometrical figures, namely ill-defined circles and lines of a certain curvature. Both processors consists of one processing element (PE) per pixel. In the first one 28,160 PEs operate on a 176×160 image. It is assembled of 22×20 semi-custom VLSI chips containing 8×8 PEs each. The processor has been in operation at CERN, Geneva, since spring 1991. The second processor finds and counts in an image all circle segments with a common vertex point within 5 μs. It is based on a Hough transform that maps the image ́s polar coordinates onto the coordinates radius of curvature and starting angle of a track, and on cluster counting executed in parallel via the Euler relation. The systolic array executing the Hough transform is composed of sixteen X3042 Xilinx chips. The Euler processor has been mapped into a single X3042 chip. The third system is a systolic special-purpose processor for low-level image and signal processing tasks. It is assembled of VLSI components which contain three identical processing elements each that all execute the basic operation multiply-and-add within one cycle of a central 40 MHz clock.